Full Report
The RP2350 by Raspberry Pi is a MicroController Unit (MCU) chip that provides a root of trust for larger systems, with tools like secure boot. This article explains the chip's security design and how it was defeated in several ways. The RP2350 is a dual-core, dual-architecture MCU with on-chip SRAM and OTP fuses. The chip contains an Cortex-M33 processor that implements TrustZone-M for secure world and non-secure world computing. There are one-time programmable Fuses (OTP) for storing root-of-trust information. There is a glitch detector that runs in 4 physically separate locations that works by detecting manipulation in the clock or voltage. Finally, there is a redundancy co-processor that executes all code in parallel, ensuring deterministic execution and protection against fault injection. For further FI protections in software, there are stack canaries, instruction delays to make FI less consistent, and integer/boolean value validation. The first security issue is around the reading of OTP Power-On State Machine (PSM). To prevent glitching the IPS voltage line, guard reads are in place; if a specific value isn't read before the real value, then the read must be corrupted. The OTP Power Supply (IPS) saves the read data during a power failure, as long as the power remains off. When this happens, the data are interpreted as the value on the IPS line! By carrying forward the guard word, this becomes a major problem. Once the data is read out, it's written back to the OTP rows. By chance, the guard word 0x333333 is written back to the CRIT1 and CRIT2 OTP rows, changing the chip's security. This disables secure boot, bypassing the chip's security. Additionally, DEBUG_DISABLE is also disabled, giving full debug access to the chip. This issue was found by dynamically debugging the chip and observing the results. Pretty neat! Much of the bootloader contains code with hardened checks that assume glitching. For instance, double-checking values, XORing magic values, and many other things are done. By reviewing the ASM of the bootloader, they found a primitive that, when specific instructions were skipped via glitching, allowed them to jump to an arbitrary location in RAM. By loading a malicious firmware into memory, this could be used to load an arbitrary binary. They attempted to do these in order of least difficult. First, they used a debugger on the chip to see whether skipping these instructions would allow their attack to work. Next, they performed the attack both with and without glitch detection. Although the glitch detections prevented the attack most of the time, successful glitches still got through. They think this is because the glitch could be so minor and still succeed. Overall, an interesting attack and good discovery via code review. The next attack uses laser fault injection to create localized errors not detected by the built-in defenses. Their target was the hashing process of loading in the firmware to be verified. Since QSPI flash can be swapped in, it's possible to create TOCTOU bugs on verified vs. executed firmware in conjunction with FI. They found several locations where a successful glitch caused unauthorized code to run. The next attack was another quick glitch in the reading of OTP values. OTP pages are configured to be readable by the firmware but NOT by the otp commands that an attacker could run. This is done by reading the SW_LOCK fuse twice. The code performs left and right 28-bit shifts to clear the upper bits of the locked value. If the right-shift instruction is skipped, then the OTP value will have a corrupted value and the SW_LOCK write to OTP is skipped. This read is performed twice with randomized time delays, but it is still doable with an Electromagnetic fault injection setup. This allows using the OTP boot to read fuses that shouldn't be accessible. The fuses are assumed to be unreadable. Their final attack is to read the fuse data directly from the fuse memory array. They found that Passive Voltage Contrast (PVC) could be used to read the antifuse bitcell memory. A little over my head, but still interesting research. They have a few takeaways: Effectiveness of Hardware Mitigations. Two of their techniques bypass these protections altogether, while others were able to work around the restrictions. These make the attack harder to pull off, but not impossible. The Dangers of Complicated Boot Paths. Bootrom and bootloaders should be minimal to minimize the primitives for exploitation. Other features should be added to a later stage. I personally really enjoyed this research paper, though I did need to learn a lot of the concepts. Still, there's a constant cat-and-mouse game between hardware protections and attackers that hasn't been resolved yet. Great read!
Analysis Summary
# Vulnerability: RP2350 Root of Trust Bypass via Fault Injection and OTP Corruption
## CVE Details
- **CVE ID:** CVE-2024-45310 (Commonly associated with the RP2350 "OTP Bootloader" flaw)
- **CVSS Score:** N/A (Hardware-level vulnerabilities often lack standard CVSS scores, but impact is Critical)
- **CWE:** CWE-1262 (Improper Lane/Physical Protection), CWE-693 (Protection Mechanism Failure), CWE-367 (TOCTOU)
## Affected Systems
- **Products:** Raspberry Pi RP2350 Microcontroller (found on Raspberry Pi Pico 2).
- **Versions:** Initial production release (Step A2).
- **Configurations:** Systems utilizing Secure Boot, OTP-based Root of Trust, and TrustZone-M for secure world isolation.
## Vulnerability Description
The RP2350’s security architecture is compromised through several physical and logic-based attack vectors:
1. **OTP Power-On State Machine (PSM) Corruption:** A flaw in the Power Supply (IPS) logic allows a "guard word" (0x333333) used to detect corruption to be incorrectly written back to the CRIT1 and CRIT2 OTP rows during specific power/glitch scenarios. This results in the accidental disabling of `SECURE_BOOT` and `DEBUG_DISABLE`.
2. **Instruction Skipping (Fault Injection):** Despite hardware glitch detectors and a redundancy co-processor, specific instruction skips in the Bootrom ASM allow jumping to arbitrary RAM locations.
3. **OTP SW_LOCK Bypass:** A logic error in how the firmware checks the `SW_LOCK` fuse. The code uses bit-shifting to validate access; if a right-shift instruction is skipped via Electromagnetic Fault Injection (EMFI), the lock is not applied, exposing sensitive fuses.
4. **Time-of-Check Time-of-Use (TOCTOU):** The QSPI flash loading process is vulnerable to firmware swapping between the hashing/verification phase and the execution phase when combined with localized Fault Injection (FI).
## Exploitation
- **Status:** PoC available (Demonstrated by researchers via dynamic debugging and physical FI).
- **Complexity:** High (Requires specialized hardware for Glitching, EMFI, or Laser Fault Injection).
- **Attack Vector:** Physical (Requires hands-on access to the chip or the ability to manipulate voltage/clock lines).
## Impact
- **Confidentiality:** High (Extraction of secret keys/fuses via EMFI or Passive Voltage Contrast).
- **Integrity:** High (Bypass of Secure Boot allows loading unauthorized/malicious firmware).
- **Availability:** High (Ability to permanently alter OTP rows or take control of the MCU).
## Remediation
### Patches
- **Hardware Revision:** As this is a hardware/Bootrom-level flaw, it cannot be patched via software update for existing silicon. Future iterations of the RP2350 may include hardware-level fixes for the PSM logic.
- **Software Hardening:** Raspberry Pi has updated SDKs to improve software-side FI mitigations, though the fundamental Bootrom primitives remain in current hardware.
### Workarounds
- **Physical Obfuscation:** Encapsulating the MCU in epoxy or using anti-tamper enclosures to prevent EMFI and Laser Fault Injection.
- **Minimal Boot Path:** Reducing the complexity of the boot process to limit the window for Fault Injection.
## Detection
- **Indicators of Compromise:** Unexpected enabling of Debug ports on production units; checksum failures in OTP CRIT rows; presence of non-signed firmware in memory.
- **Detection Methods and Tools:** Side-channel analysis and monitoring for voltage/clock fluctuations that trigger the internal glitch detectors.
## References
- **Vendor Advisories:** hxxps[://]www[.]raspberrypi[.]com/documentation/microcontrollers/rp2350[.]html
- **Research Link:** hxxps[://]github[.]com/raspberrypi/pico-sdk (Relevant for SDK hardening updates)
- **Technical Analysis:** hxxps[://]www[.]tomshardware[.]com/raspberry-pi/raspberry-pi-confirms-rp2350-hardware-bug (General reporting on the flaw)