Full Report
Attackers would need physical access to the server to pull off the DDR5 trick
Analysis Summary
# Vulnerability: DDRop - Active Memory Interposer Attack on DDR5
## CVE Details
- **CVE ID**: Not yet assigned (Disclosed September 2026).
- **CVSS Score**: Estimated 4.3 to 5.2 (Medium). *Note: While the impact is high, the physical access requirement significantly lowers the CVSS score.*
- **CWE**: CWE-441: Unintended Proxy or Intermediary (Hardware Design Flaw / Lack of Freshness Checks).
## Affected Systems
- **Products**: Servers utilizing Scalable Memory Encryption within Trusted Execution Environments (TEEs).
- **Versions**:
- Intel Trust Domain Extensions (TDX)
- Intel Scalable Software Guard Extensions (SGX)
- AMD Secure Encrypted Virtualization-Secure Nested Paging (SEV-SNP)
- **Configurations**: Systems using DDR5 memory modules where the hardware architecture trades cryptographic freshness for scalability.
## Vulnerability Description
The DDRop attack exploits a design flaw in modern scalable memory encryption hardware. To support large amounts of encrypted memory in cloud environments, vendors opted not to implement full "cryptographic freshness" checks (which ensure data has not been replaced by older versions).
Using a custom hardware interposer placed between the CPU and the DDR5 RAM, attackers can intercept and "drop" write commands. Because the system fails to verify if the data is current, the protected Virtual Machine (VM) continues to operate using stale, encrypted data that still decrypts perfectly. This allows for replay attacks against encrypted memory at full bus speeds.
## Exploitation
- **Status**: PoC available (Open-source hardware design released).
- **Complexity**: High (Requires custom hardware fabrication and precise physical installation).
- **Attack Vector**: Physical (Requires direct access to the server motherboard/DDR5 slots).
## Impact
- **Confidentiality**: High (Attackers can force VMs into debug mode to read private memory in plaintext).
- **Integrity**: High (Enables forging of attestation reports and injection of malicious secure page-table entries).
- **Availability**: Low (The attack is deterministic and designed to avoid system crashes).
## Remediation
### Patches
- **No current patches available**: The vulnerability is rooted in the hardware design of the memory controller and DDR5 command bus handling.
- **Intel/AMD Stance**: Both vendors have currently labeled this attack as "out of scope" for their standard cloud threat models, as it requires physical hardware tampering.
### Workarounds
- **Physical Security**: Enhanced data center security, including chassis intrusion detection and tamper-evident seals.
- **Boot-time Attestation**: While the attack can forge reports, rigorous external monitoring of hardware configurations may mitigate risks.
## Detection
- **Indicators of Compromise**: Difficult to detect via software as the interposer operates at the hardware layer and does not crash the machine.
- **Detection Methods**:
- Physical inspection of the DDR5 DIMM slots for unauthorized interposer hardware.
- Potential future "cache line versioning" or architectural hardening currently being evaluated by Intel.
## References
- Intel Security Announcement (2026-08-11-001): [hXXps://www.intel.com/content/www/us/en/security-center/announcement/intel-security-announcement-2026-08-11-001.html]
- DDRop Research Site: [hXXps://ddropattack.eu/]
- Technical Paper: [hXXps://github.com/ddropattack/ddrop]
- TEE.fail Comparison: [hXXps://tee.fail/]